5,6,7nm Memory Product (FF+ GL, FF+ LL, FFC)

 

Single and Dual Port SRAM with both Row and Column redundancy with Following Low Power options:

• Low Leakage with retention (light and deep sleep)

• Power Gating with retention and without retention

• Dual Rail (SRAM Periphery at lower Voltage)

• Combinations of above low power options

1-Port and 2-port Register File with Column redundancy and all the above Low power options

Pseudo 2-Port Register Files Compiler

Multi-Banking Single Port SRAM compiler for larger SRAMs

ROM Compiler

TCAM & BCAM

Low Power Register Files Tiles to created low leakage memory blocks

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Low Power Mode Support

• Dual Power Rail: Memories with separate periphery and memory array power domains to save both dynamic and static power

• Ultra Low Leak: Lower leakage while retaining contents of memory using light sleep or deep sleep mode

• Power Gating: Provides absolute lowest leakage by turning off the power. Memory contents are not retained

 

Multi Banking Support

• Generate larger instances(up to 2Mbits)

• The memories are banked with the logic shared, to provide with the most area efficient solution for larger memory blocks

 

Memory BIST and Repair

• BIST solution optimized to our memories